Adder merged DRAM architecture

Abstract

A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.