XTP in VLSI protocol decomposition for ASIC implementation

Abstract

The provision of VLSI support for protocols is viewed as an exercise in decomposition of protocol processing. The Xpress transfer protocol (XTP) is described as a representative protocol with some new features. A general-purpose VLSI architecture is described that supports XTP and other protocols. It is shown how the coupled protocol engine hardware and XTP protocol design achieves data rivering rates for multiple protocols at previously unachievable price performance levels.<>