Deep subhalf-micron BiCMOS technology using synchrotron X-ray lithography and its application to 58 ps 2 V CMOS gate array

Abstract

Deep sub-half-micron BiCMOS technology using synchrotron X-ray lithography and two-level metallization featuring planarization and selective CVD Al plugs is described. The process achieves a 0.24- mu m-wide first wiring resist pattern and contact resistivity of 5*10/sup -10/ Omega -cm/sup 2/ for a 0.25- mu m via hole. A 4 K-gate 0.25- mu m CMOS gate array LSI that operates at 58 ps/gate at 2 V was fabricated. This result demonstrates the efficacy of synchrotron X-ray lithography in the fabrication of sub-quarter-micron BiCMOS ULSIs.<>