{"title":"An ultralow-power high-gain biopotential amplifier for electromyogram signal recording","authors":"Ehab A. Hamed, M. Atef, M. Abbas","doi":"10.1109/JEC-ECC.2017.8305772","DOIUrl":null,"url":null,"abstract":"This paper introduces a design for an ultralow-power electromyogram (EMG) signal amplifier with low noise operation. The design consists of two stages, the first stage is highly efficient but supply-sensitive single ended amplifier and the second stage is differential, to improve the supply rejection ratio and common mode rejection ratio. Each stage is configured with cascode MOSFET transistors to increase the gain value. The proposed design is simulated by 130 nm CMOS, and its results are reported. The design achieves 60.62 dB mid-band gain with bandwidth of 1.72kHz. Using a supply voltage of 1.1 V, the amplifier consumes 1.03 μA of current. Input referred noise is 3.006 μVrms. The common mode and power supply rejection ratios are above 49.05 dB and 55.72 dB respectively.","PeriodicalId":406498,"journal":{"name":"2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/JEC-ECC.2017.8305772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper introduces a design for an ultralow-power electromyogram (EMG) signal amplifier with low noise operation. The design consists of two stages, the first stage is highly efficient but supply-sensitive single ended amplifier and the second stage is differential, to improve the supply rejection ratio and common mode rejection ratio. Each stage is configured with cascode MOSFET transistors to increase the gain value. The proposed design is simulated by 130 nm CMOS, and its results are reported. The design achieves 60.62 dB mid-band gain with bandwidth of 1.72kHz. Using a supply voltage of 1.1 V, the amplifier consumes 1.03 μA of current. Input referred noise is 3.006 μVrms. The common mode and power supply rejection ratios are above 49.05 dB and 55.72 dB respectively.