{"title":"FPGA based control of quasi resonant DC-link inverter and induction motor drive","authors":"J. Kedarisetti, P. Mutschler","doi":"10.1109/ISIE.2011.5984394","DOIUrl":null,"url":null,"abstract":"An indirect field oriented controlled induction machine is driven by quasi resonant DC-link soft switching inverter (QRDCLI). The total control of a soft switching inverter together with the motor has been realized in a single chip FPGA (Field Programmable Gate Array). It reduces the total hardware count and provides low cost solution. The control algorithm has decomposed into several blocks. All the blocks execute in parallel with individual sampling rates. For the soft switching inverter bridge control, the modified space vector PWM (SVPWM) technique is implemented in FPGA.","PeriodicalId":162453,"journal":{"name":"2011 IEEE International Symposium on Industrial Electronics","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Symposium on Industrial Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIE.2011.5984394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
An indirect field oriented controlled induction machine is driven by quasi resonant DC-link soft switching inverter (QRDCLI). The total control of a soft switching inverter together with the motor has been realized in a single chip FPGA (Field Programmable Gate Array). It reduces the total hardware count and provides low cost solution. The control algorithm has decomposed into several blocks. All the blocks execute in parallel with individual sampling rates. For the soft switching inverter bridge control, the modified space vector PWM (SVPWM) technique is implemented in FPGA.