High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

Abstract

A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good Ron capabilities (~1Omega). The protection of high voltage I/Os with a narrow ESD design window ranging from 80 V to 100 V can be implemented in a reduced surface of 151*140 mum2, which represents a state-of-the-art breakthrough.