An area-efficient and degree-computationless BCH decoder for DVB-S2

Abstract

This paper presents an area-efficient BCH decoder for DVB-S2 system. The proposed architecture can support all 11 code rates in DVB-S2. Based on the modified Euclidean algorithm (MEA), The BCH decoder has a low hardware complexity with the folding and degree computationless architecture in key equation solver (KES) block. Further more, the multiplier in Galois Field is also optimized to reduce the hardware complexity. The proposed decoder requires at least 16% fewer gates than the conventional RS/BCH decoders and can work up to 277MHz, which meets the speed requirements of the system1.