A dynamically reconfigurable asynchronous processor

Abstract

The main design requirements for high-throughput mobile applications are energy efficiency and programmability. This paper presents a novel dynamically reconfigurable processor that targets these requirements. Our processor consists of a heterogeneous array of coarse grain asynchronous cells. The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability via conventional high-level languages. Results show that our processor delivers considerably lower power consumption when compared to a market leading VLIW and a low-power ARM processor, while maintaining their throughput performance. For example, our processor resulted in a reduction in power consumption over the ARM7 processor of over 9 times when running the bilinear demosaicing algorithm at the same throughput. Our processor was also compared to an equivalent synchronous design, resulting in a power reduction of up to 15%.