A dynamically reconfigurable asynchronous processor

Khodor Ahmad Fawaz, T. Arslan, S. Khawam, M. Muir, I. Nousias, Iain A. B. Lindsay, A. Erdogan
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引用次数: 3

Abstract

The main design requirements for high-throughput mobile applications are energy efficiency and programmability. This paper presents a novel dynamically reconfigurable processor that targets these requirements. Our processor consists of a heterogeneous array of coarse grain asynchronous cells. The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability via conventional high-level languages. Results show that our processor delivers considerably lower power consumption when compared to a market leading VLIW and a low-power ARM processor, while maintaining their throughput performance. For example, our processor resulted in a reduction in power consumption over the ARM7 processor of over 9 times when running the bilinear demosaicing algorithm at the same throughput. Our processor was also compared to an equivalent synchronous design, resulting in a power reduction of up to 15%.
动态可重构的异步处理器
高吞吐量移动应用程序的主要设计要求是能效和可编程性。针对这些需求,本文提出了一种新的动态可重构处理器。我们的处理器由一组粗粮异步单元组成。该体系结构保留了自定义异步设计的大部分优点,同时还通过传统的高级语言提供可编程性。结果表明,与市场领先的VLIW和低功耗ARM处理器相比,我们的处理器提供了相当低的功耗,同时保持了它们的吞吐量性能。例如,在相同吞吐量下运行双线性反马赛克算法时,我们的处理器使功耗比ARM7处理器降低了9倍以上。我们的处理器还与同等的同步设计进行了比较,结果功耗降低了15%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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