On resilience of security-oriented error detecting architectures against power attacks: a theoretical analysis

Abstract

It has been previously shown that hardware implementation of fault attack countermeasures based on error-detecting codes (EDCs) can make the circuit more vulnerable to power analysis attacks. We revisit this finding and show that the hypothesis space can grow significantly when a state-of-the-art security-oriented robust EDC is properly crafted. We use the Roth-Karp decomposition as an analytical tool to prove that by a simple re-ordering of the EDC's bits, the number of extra bits needed to formulate the hypotheses becomes so large that power analysis (that tries to exploit additional information from the redundant bits) is rendered infeasible.