Design and experimental verification of on-chip signal integrity analyzer (OSIA) scheme for eye diagram monitoring of a high-speed serial link

Abstract

Recently, bandwidth of data channel has increased with the development of high-performance electronic system. The method used to characterize the channel is important for successful channel design. However, conventional methods have several disadvantages to characterize the whole high-speed serial link including on-chip and package channel. In this paper, we design and experimental verification of on-chip signal integrity analyzer (OSIA) scheme for high-speed data transmission. The designed OSIA circuit can be an effective method to determine the eye diagram of an inside package channel and on-chip I/O channel because it is located at the front of a receiver circuit. The test chip for the OSIA is fabricated by a standard 0.18-μm CMOS process. The performance of the proposed OSIA is verified be measuring the eye diagram of a chip-package-board hierarchical channel with 10 ps and with 10-mV resolution. It is successfully demonstrated to monitor the eye diagram distortion affected by variation of data rate and channel loss.