Electrical and microstructures properties of polygate electrode in 0.5 /spl mu/m CMOS devices

Abstract

The effect of phosphorus, doped in-situ and by ion implantation on polysilicon, as a gate electrode of 0.5 /spl mu/m CMOS was investigated. The result shows that two-step annealing is required to cure the radiation damage and activate the dopant in reducing the sheet resistance of the ion implanted gate electrode. The introduction of phosphorus from 7/spl times/10/sup 15/ to 3/spl times/10/sup 16//cm/sup 3/ by ion implantation at 40 keV has reduced the sheet resistance from 100 /spl Omega///spl square/ to 25 /spl Omega///spl square/, comparable to the gate produced by in-situ phosphorus doping. The polysilicon gate electrode microstructures were studied using TEM, and it was found that grains of samples in in-situ doped polysilicon are larger than in other samples.