Operation Scheme Optimization for Charge Trap Transistors (CTTs) Based on Fully Depleted Silicon-On-Insulator (FDSOI) Platform

Abstract

Recently, the charge trap transistors (CTTs) based on CMOS logic devices have been actively explored. The charges in the CTT gate stack could be injected by the hot carrier (HC) effect and removed by changing the polarity of the gate electric field, which can be used as the “program” and “erase” operations for memory applications. In this work, the performance of the FDSOI CTT under various program voltages has been investigated. It is found that when the devices are under moderate horizontal acceleration (the bias voltage $V_{\mathrm{D}}=1/2V_{\mathrm{G}}$), the CTT shows better performance uniformity and reliability. In addition, the related working mechanism and an optimized operation scheme have also been proposed.