{"title":"CORDIC rotator for frequency translation","authors":"A. I. Smekalov, V. Djigan","doi":"10.1109/EWDTS.2016.7807701","DOIUrl":null,"url":null,"abstract":"This paper presents a digital frequency translation by the CORDIC rotator (COordinate Rotation DIgital Computer) which does not require a complex multiplier and a phase-to-exponent converter. The CORDIC algorithm overview and detailed implementation architecture are presented. The architecture is fitted to implementation in high speed designs and using in Application-Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA). The simulation results demonstrate the performance of proposed frequency translator in terms of Normalized Mean-Square Error (NMSE) and spectral purity. The proposed architecture requires about 79 times less resources compared to the conventional approach with a complex multiplier and Numerically Controlled Oscillator (NCO) at the same level 98 dB of Spurious Free Dynamic Range (SFDR).","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2016.7807701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a digital frequency translation by the CORDIC rotator (COordinate Rotation DIgital Computer) which does not require a complex multiplier and a phase-to-exponent converter. The CORDIC algorithm overview and detailed implementation architecture are presented. The architecture is fitted to implementation in high speed designs and using in Application-Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA). The simulation results demonstrate the performance of proposed frequency translator in terms of Normalized Mean-Square Error (NMSE) and spectral purity. The proposed architecture requires about 79 times less resources compared to the conventional approach with a complex multiplier and Numerically Controlled Oscillator (NCO) at the same level 98 dB of Spurious Free Dynamic Range (SFDR).