Performance Evaluation of Optimum Number of Stages for ADPLL Ring Oscillator

Abstract

An all-digital phase-locked loop (ADPLL) has been demanded among academics and industries due to its advantages in the complementary-metal-oxide semiconductor (CMOS) technology process. In the ADPLL, one of the crucial blocks is the digital-controlled oscillator (DCO), which is a combination of the digital-to-analog converter (DAC) and the voltage-controlled oscillator (VCO). In this work, the approach of the CMOS inverter ring oscillator is designed using Cadence OrCad Capture with CMOS 90 nm technology process. The ring oscillator is designed with different stages, which are 3-stage, 5-stage, and 7-stage configurations. At the output of every stage, a 0.001pF capacitor is connected as a capacitance load. The result shows that the oscillation period started for the 7-stage is 0.1 ns, which is faster than the 5-stage and the 3-stage of the ring oscillator, which are 0.6 ns and 0.15, ns respectively. For the power consumption performance, the 3-stage recorded $52.47 \mu \mathrm{W}$ which is the lowest power dissipated compared to others.