Low-frequency noise in bare SOI wafers: Experiments and model

Abstract

Noise measurements are efficient for interface trap density characterization in MOSFETs and can be extended to bare silicon-on-insulator wafers. A physical model to explain the experimental results will be presented. The impact of measurement parameters, like die area and probe distance, is discussed comparing experimental and calculated characteristics. Important clarifications concerning the effective die area contributing to noise response will be pointed out.