Reliability Optimization of ReRAM Architecture using Heterogeneous Error Correcting Code Scheme

Abstract

The memristor-based resistive random access memory (ReRAM) has been emerged because of its beneficial properties such as non-volatility, high density, and process scalability. However, ReRAM also suffers from process variation caused by down scaling of device size and operating voltage level. In this paper, we propose a new reliable ReRAM architecture with heterogeneous ECC-based subblock architecture focusing on reducing implementation overhead. Experimental results show that the proposed approach reduces the number of parity bits by 18.80 %, area by 20.43 %, respectively, and increases the code rate by 3.90 % compared to those of conventional homogeneous ECC scheme.