Hector Andrade, Aaron Maharry, Luis A. Valenzuela, Navid Hosseinzadeh, C. Schow, J. Buckwalter
{"title":"An 8.2-pJ/bit, 56 Gb/s Traveling-wave Modulator Driver with Large Reverse Terminations","authors":"Hector Andrade, Aaron Maharry, Luis A. Valenzuela, Navid Hosseinzadeh, C. Schow, J. Buckwalter","doi":"10.1109/BCICTS50416.2021.9682462","DOIUrl":null,"url":null,"abstract":"This paper presents a 56 Gb/s traveling-wave Mach-Zehnder Modulator (TW-MZM) driver fabricated in the GlobalFoundries 8XP 130-nm SiGe BiCMOS process employing a cascode topology. The quasi-open collector design delivers a 4.4 ${{\\mathrm{V}}_{\\text{pp}}}$ differential swing and reduces the amplitude of the secondary reflections while maintaining a low overall power consumption of 460 mW, or 8.2 pJ/bit at 56 Gb/s, including the modulator termination resistance dissipation. The driver has two variants, each of which provides a different TW-MZM biasing scheme, to enable operation at two different PN junction phase shifter biases. Eye-diagrams at up to 60 Gb/s are presented as well as bit-error rate (BER) bathtub curves.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS50416.2021.9682462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a 56 Gb/s traveling-wave Mach-Zehnder Modulator (TW-MZM) driver fabricated in the GlobalFoundries 8XP 130-nm SiGe BiCMOS process employing a cascode topology. The quasi-open collector design delivers a 4.4 ${{\mathrm{V}}_{\text{pp}}}$ differential swing and reduces the amplitude of the secondary reflections while maintaining a low overall power consumption of 460 mW, or 8.2 pJ/bit at 56 Gb/s, including the modulator termination resistance dissipation. The driver has two variants, each of which provides a different TW-MZM biasing scheme, to enable operation at two different PN junction phase shifter biases. Eye-diagrams at up to 60 Gb/s are presented as well as bit-error rate (BER) bathtub curves.