Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach

Abstract

In shared-memory multi-processor systems on chip for media processing, the access to off-chip memory is often a critical resource. The memory channel is shared by a mix of streams with timing requirements at different levels. The streams are arbitrated in the memory access network. Some streams have to meet a hard deadline for each transaction; other streams have to meet task-level execution-time constraints, where task execution times depend on the service received when performing memory accesses. Earlier work has resulted in arbitration algorithms that provide the necessary balance between the different stream types, allowing aggressive system design with a high utilization of the memory access path. The next challenge is to provide real-time analysis in an early stage of system design. To address this challenge, this paper proposes a practical approach that combines proven analytical methods with fast simulations. The approach provides a design space from which to choose arbiter settings and buffer sizes for memory-communication buffers.