Energy-efficient implementation of AES algorithm on 16nm FPGA

Abstract

Cryptographic algorithms ensure security of data in CPSs, IoT and SCADA systems and platforms. Some researchers ascertained that the security processes have extensive effects on battery life of a device and FPGAs present a novel resolution for augmenting the performance of devices and the AES algorithm offers means to secure data transmission. In this research, we have analyzed the power consumption of the AES algorithm on 16nm Kintex Ultrascale+ FPGA for 5 different IO Standards to determine the least power consuming and an energy efficient architecture for its implementation. We have used Xilinx Vivado 2018.2 ISE for all the observations done in this work. Out of 5 IO Standards analyzed, POD12 and HSTL_I_12 IO Standards consumed least power and LVCMOS consumed maximum power. At output load of 10000pF, there is 94.92% savings in total on-chip power utilization when we migrate our design from LVCMOS18 to HSTL_I_12 and 94.88% savings in total on-chip power utilization when we migrate our design from LVCMOS18 to POD12. For further reducing the power consumption, different Green Computing techniques like frequency scaling, thermal scaling, clock gating etc can be applied. We may also execute our work on 3-D and 4-D ICs. The outcomes gained in this paper can assist in a more energy efficient FPGA implementation of AES.