Integrated Circuit Die Level Yield Prediction Using Deep Learning

Abstract

Given the integrated circuits (IC) production scale, the amount of process control monitoring (PCM) data enable to develop an efficient algorithm for IC yield prediction at the die-level. Therefore, in addition to cost-effective and time-efficient yield evaluation, the proposed model is able to identify failed dice and low-yield areas on a wafer without any direct electrical die testing. Additionally, for non-parametric random dice failure detection that are untraceable by PCM input based models, an ensemble learning including both PCM and die defect inspection data are described. As Wafer Sort (WS) consumes a lot of time and resources with high associated cost a significant cost reduction can be achieved using smart product routing with selective WS by employing the aforementioned die level predictive model.