P. Szecówka, M. Kowalski, K. Krysztoforski, A. Wolczowski
{"title":"Wavelet Processing Implementation in Digital Hardware","authors":"P. Szecówka, M. Kowalski, K. Krysztoforski, A. Wolczowski","doi":"10.1109/MIXDES.2007.4286243","DOIUrl":null,"url":null,"abstract":"The paper describes an architecture and design of digital circuit dedicated for wavelet transform calculation, being a part of complex pattern recognition and control algorithm. The target application is artificial hand controlled by the nervous system of handicapped human, setting strict requirements on timing. Speed/size trade-off is discussed in general and in the context of this particular application. Floating point arithmetic was applied, based on the in-house developed solutions. The concept was implemented using VHDL, verified and successfully synthesized for FPGA programmable logic.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286243","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The paper describes an architecture and design of digital circuit dedicated for wavelet transform calculation, being a part of complex pattern recognition and control algorithm. The target application is artificial hand controlled by the nervous system of handicapped human, setting strict requirements on timing. Speed/size trade-off is discussed in general and in the context of this particular application. Floating point arithmetic was applied, based on the in-house developed solutions. The concept was implemented using VHDL, verified and successfully synthesized for FPGA programmable logic.