Defect cluster segmentation for CMOS fabricated wafers

Abstract

IC defects, which are essentially present in all fabricated wafers, can either be random defects or belonging to a group of systematic defects. The ability to segment systematic defects that are present in a wafer allows rapid root cause identification and corrective measures to be taken. In this paper, we have developed an algorithm based on the connected-components labeling to perform defect cluster segmentation. Dilation and erosion procedure is performed prior to the labeling process to eliminate isolated random defects in the wafer. A thresholding method which involves manual analysis by an industrial specialist is discussed. The advantage of this method is the ease and speed of implementation, and its robustness in allowing fine-tuning that suits the intended application.