M. Togashi, S. Sato, S. Ohshima, K. Aruga, T. Nakamura
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引用次数: 4
Abstract
This paper will cover a 5.7mm × 5.73mm chip with 9000 transistors using 3μm CMOS technology and a dissipation of 200mW. The processor incorporates an on-chip 6b parallel ADC and achieves 3% correction accuracy at a 1MHz conversion rate.