Clock skew automation for power and area reduction in deep sub micron designs

Abstract

The importance of the metrics of power vs. performance and area vs. performance can hardly be overstated in the context of timing closure on deep submicron designs. This paper describes how useful clock skew is handled post placement to fix timing without compromising the robustness of the clock tree. A novel method of automation is proposed where useful skew is calculated and applied across the design after evaluating the impact of skew introduction on multiple modes and corners, a limiting factor for most production tools. It is described further how the technique was deployed on a 45 nm multi-million gate imaging subsystem to improve power by 50% and area by as much as 90% in portions of the design. The paper concludes with a comparison of results from traditional setup and hold fixing vs. useful skew adjustment.