Evaluation of FinFET in Ultra Low Power ALU

Abstract

The data path and memory elements are integral hardware components to evaluate the performance of a complex ASIC low power architecture. In this study, a FinFET model was evaluated via 7 nm FinFET process using ASAP PDK and applied to 6T SRAM cells and 32-bit ALU architecture. Devices of 0.207 V threshold were biased at 0.7V supply voltage. The clock router was properly modeled with accurate values of resistances and capacitances for the metal layers. The noise glitch and cross talk within the parallel running interconnects and the driving loads were incorporated in the model. A command set clock uncertainty is also integrated into the model to incorporate the clock jitter and clock skew effects. The architecture was optimized for worst case scenario with typical RC corners. The Non-Linear Delay Model (NLDM) was incorporated for the cell synthesis where a delay that is based on the input transition and output load capacitance was incorporated for better quality of results (QoR). The low power architecture was evaluated for worst case scenario considering typical-typical (TT) corners. A maximum effective device current of 18.26µA with subthreshold slope of 60mV/decade were estimated and considered in the system evaluation. The output ports were loaded with a typical 2fF capacitance. At 1 GHz operation, the internal power, switching power, and leakage power are reported to be 0.2705 mW, 0.7599 mW, and 0.00743 mW, respectively.