0.6 /spl mu/m CMOS technology with radiation tolerant features application to 8 K/spl times/16 dual port RAM and sea of gates

Abstract

After recalling options selected to harden a 0.6 /spl mu/m CMOS technology against the two major radiation concerns of the space environment, total dose and heavy ion induced latch-up, thus highlighting the dual use approach in place at MATRA MHS, the authors report data gathered during radiation tests of dual port RAM and sea of gates circuits. The impact of the dimension of various storing elements on the upset sensitivity is assessed. Finally, with regard to the trend of reducing global power consumption of spaceborne applications while increasing overall performance, the pro and cons of using a reduced 3.3 V power supply are explored.