Jayanand Asok Kumar, K. Butler, Heesoo Kim, Shobha Vasudevan
{"title":"Early prediction of NBTI effects using RTL source code analysis","authors":"Jayanand Asok Kumar, K. Butler, Heesoo Kim, Shobha Vasudevan","doi":"10.1145/2228360.2228506","DOIUrl":null,"url":null,"abstract":"In present day technology, the design of reliable systems must factor in temporal degradation due to aging effects such as Negative Bias Temperature Instability (NBTI). In this paper, we present a methodology to estimate delay degradation early at the Register Transfer Level (RTL). We statically analyze the RTL source code to determine signal correlations. We then determine probability distributions of RTL signals formally by using probabilistic model checking. Finally, we propagate these signal probabilities through delay macromodels and estimate the delay degradation. We demonstrate our methodology on several benchmarks RTL designs. We estimate the degradation with <;10% error and up to 18.2× speedup in runtime as compared to estimation using gate-level simulations.","PeriodicalId":263599,"journal":{"name":"DAC Design Automation Conference 2012","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"DAC Design Automation Conference 2012","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2228360.2228506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In present day technology, the design of reliable systems must factor in temporal degradation due to aging effects such as Negative Bias Temperature Instability (NBTI). In this paper, we present a methodology to estimate delay degradation early at the Register Transfer Level (RTL). We statically analyze the RTL source code to determine signal correlations. We then determine probability distributions of RTL signals formally by using probabilistic model checking. Finally, we propagate these signal probabilities through delay macromodels and estimate the delay degradation. We demonstrate our methodology on several benchmarks RTL designs. We estimate the degradation with <;10% error and up to 18.2× speedup in runtime as compared to estimation using gate-level simulations.