Selecting the right cache architecture for high performance PCS

Abstract

The characteristics of asynchronous SRAMs have led SRAM vendors to provide new SRAM architectures with simpler interfaces in order to improve system performance. One of the new architectures that is becoming an industry standard for the second level cache (L2) for the Intel Pentium processor is a 32K/spl times/32 pipeline burst mode SRAM. The architecture, backed by Intel and multiple SRAM vendors, is an effort to standardize the 32K/spl times/32 burst mode SRAM and system design interface for a second level cache (L2) for the Pentium processor.<>