SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology

Abstract

This paper presents a comparative analysis of radiation sensitivity and SET mitigation techniques for the Mirror Full Adder topology implemented with FinFET devices at 7 nm node, considering nominal and near-threshold operation. The mitigation techniques investigated are Decoupling Cells and Transistor Sizing. Transistor Sizing may improved robustness up to $2\mathrm{x}$ (nominal) and close to $3\mathrm{x}$ (near-threshold). Combining the techniques decreases the total error occurrence close to 60% at nominal operation and up to 34% at near-threshold operation.