Failure Analysis for SIP IC EOS fail

Abstract

A System-In-Package (SIP) circuit displayed a hard failure once deployed. After decapsulation, visible damages could be observed in one corner of the chip. as if some local burning occurred. Structural analysis of the device using 3D-Xray and slice analysis, revealed that it was constituted of two parallel structures. burning should be random in theory. Missing silver paste adhesive filling was identified as a root cause for this damage. Further investigations through X-ray imaging showed that the chip was not fully welded. Since the device can reach very high temperature during operation, the lack of silver paste adhesive led to poor power dissipation in some area which translated in damages.