F. Gianesello, A. Monroy, V. Vialla, E. Canderle, G. Bertrand, M. Buczko, M. Coly, Jeff Nowakowski, N. Revil, L. Rolland, D. Gloria, A. Juge, S. Gachon, J. Aubert, E. Granger
{"title":"Highly linear and sub 120 fs Ron × Coff 130 nm RF SOI technology targeting 5G carrier aggregation RF switches and FEM SOC","authors":"F. Gianesello, A. Monroy, V. Vialla, E. Canderle, G. Bertrand, M. Buczko, M. Coly, Jeff Nowakowski, N. Revil, L. Rolland, D. Gloria, A. Juge, S. Gachon, J. Aubert, E. Granger","doi":"10.1109/SIRF.2016.7445454","DOIUrl":null,"url":null,"abstract":"RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has emerged over the past few years as the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology are already exceeding what was feasible using GaAs one, new cellular system such as carrier aggregation require even more stringent performances (linearity, power handling, insertion loss, isolation). To address those new requirements, RF SOI technology has to be improved. In this paper, the performances results of the latest generations of RF SOI switch technologies from STMicroelectronics are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also proposed, paving the way for RF SOI technology able to address 5G RF switches challenges.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2016.7445454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has emerged over the past few years as the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology are already exceeding what was feasible using GaAs one, new cellular system such as carrier aggregation require even more stringent performances (linearity, power handling, insertion loss, isolation). To address those new requirements, RF SOI technology has to be improved. In this paper, the performances results of the latest generations of RF SOI switch technologies from STMicroelectronics are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also proposed, paving the way for RF SOI technology able to address 5G RF switches challenges.