Combined multiplication and sum-of-squares units

Abstract

Multiplication and squaring are important operations in digital signal processing and multimedia applications. We present designs for units that implement either multiplication, A/spl times/B, or sum-of-squares computations, A/sup 2/+B/sup 2/, based on an input control signal. Compared to conventional parallel multipliers, these units have a modest increase in area and delay, but allow either multiplication or sum-of-squares computations to be performed. Combined multiplication and sum-of-squares units for unsigned and two's complement operands are presented, along with integrated designs that can operate on either unsigned or two's complement operands. The designs can also be extended to work with a third accumulator operand to compute either Z+A/spl times/B or Z+A/sup 2/+B/sup 2/. Synthesis results indicate that a combined multiplication and sum-of-squares unit for 32-bit two's complement operands can be implemented with roughly 15% more area and nearly the same worst case delay as a conventional 32-bit two's complement multiplier.