A 2µm poly-gate CMOS analog/digital array

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156618

J. Kuo, Oh-Hyun Kwon, D. Galbraith, F. Shone, J. Shott, J. Walker, R. Dutton, J. Meindl

引用次数: 0

Abstract

The development of a 2μm poly-gate CMOS array which combines digital gate array together with stacked-layout analog capability will be covered. Up to 10 sections of a biquadratic switched-capacitor filter can be implemented in the analog section.

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2µm多栅极CMOS模拟/数字阵列

将介绍一种结合数字门阵列和堆叠布局模拟能力的2μm多门CMOS阵列的开发。双二次型开关电容滤波器最多可在模拟部分实现10段。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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