Performance Analysis of GaSb/InAs Tunnel FET for Low Power Applications

Abstract

The scaling limitations of conventional MOSFET necessitates new MOS device architecture that can operate at low voltage for low power applications. III-V heterojunction TFET has been created and its performance has been studied. The analysis has been made to choose proper values to source and drain regions doping and work functions for the gate metal electrodes. Tunnel FET device attains 51 mV/dec subthreshold swing with $I_{ON}=1.96\times 10^{-5}A;I_{OFF}=8.217\times 10^{-12}$ A.