The hierarchical h-adaptive 3-D boundary element computation of VLSI interconnect capacitance

Abstract

In deep submicron VLSI circuits, the interconnect parasitic capacitance is a very important factor determining circuit performances such as power and time-delay. The Boundary Element Method (BEM) is an effective tool for solving Laplacian's equation applied in the parasitic capacitance extraction. In this paper, a hierarchical h-adaptive BEM is presented. It constructs a 3-D linear hierarchical shape function based on a constant boundary element and uses previous computations and solutions. Hence, it reduces computation significantly in the adaptive procedure. Besides, a combination of a residual-type estimator and reduced Z-Z error estimator for more reliable and efficient estimation of error is presented. Some numerical results show that this method is effective.