Simulation Acceleration with HW Re-Compilation Avoidance

Abstract

This work is based on a premise that in traditional, simulation-based RTL functional verification reducing total debugging turnaround time (which includes both the simulation execution time and the compilation time) is much more desirable than simply increasing the simulation speed. This is due to the repeated nature of the debugging process, which includes a large number of simulation and compilation steps. While the HDL compilation process is fast, pure HDL simulation suffers from extremely long simulation execution time. On the other hand, HW-assisted simulation acceleration is characterized by fast execution, but suffers from a long HW re-compilation time, required whenever the design is modified for debugging. This paper proposes an efficient HW-assisted simulation acceleration method based on HW re-compilation avoidance, which can significantly reduce the debugging turnaround time, while maintaining its high execution speed.