A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

Abstract

This paper presents a 4X Time-Interleaved (TI) 2nd-order discrete-time (DT) ΔΣ Modulator (DSM) using digital feedforward extrapolation. Three feedforward paths digitize one channel information first and then extrapolate the other channels fully in the digital domain. Hence, this DSM only needs two opamps in one channel to realize four interleaving paths, thus reducing analog hardware overheads. With the sampling clock @ 520MHz, this 28nm CMOS prototype achieves an equivalent output sampling rate of 2.08GS/s, 208× OSR, 86.1dB SNDR, and 98dB SFDR over a 5MHz BW, while consuming 23.1mW. It results in an FOMS of 169.5dB.