Non-fractional parallelism in LDPC Decoder implementations

Abstract

Because of its excellent bit-error-rate performance, the low-density parity-check (LDPC) decoding algorithm is gaining increased attention in communication standards and literature. Also the new Chinese digital video broadcast standard (CDVB-T) uses LDPC codes. This standard uses a large prime number as the parallelism factor, leading to high area cost. This paper presents a new method to allow fractional dividers to be used. The method depends on the property that consecutive sub-circulants have one memory row in common. Several techniques are shown for assuring this property, or solving memory conflicts, making the method more generally applicable. In fact, the proposed technique is a first step towards a general purpose LDPC processor. For the CDVB-T decoder implementation the method leads to a factor 3 improvement in area