An age-aware library for reliability simulation of digital ICs

Abstract

A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account key reliability-impacting parameters such as input slew rate, output load, signal toggle rate, signal activity factor, output buffer size and age. A framework for using this age-aware library to analyze the aging of digital Integrated Circuit (IC) timing performance using existing Electronic Design Automation (EDA) methodologies is also discussed.