B. Green, V. Kaper, V. Tilak, J. Shealy, L. Eastman
{"title":"Dynamic loadline analysis of AlGaN/GaN HEMTs","authors":"B. Green, V. Kaper, V. Tilak, J. Shealy, L. Eastman","doi":"10.1109/LECHPD.2002.1146786","DOIUrl":null,"url":null,"abstract":"Surface trapping has been identified as a mechanism for lower than expected output power for experimental AlGaN/GaN HEMTs devices. This paper presents dynamic loadline analysis as a means of understanding device behavior that limits large signal performance. From observations of measured data, a model for bias-dependent drain resistance caused by trap-induced space-charge in the ungated region on the drain side of the gate is proposed. This bias-dependent drain resistance model is implemented in conjunction with a Curtice-cubic analytical transistor model to simulate the observed behavior.","PeriodicalId":137839,"journal":{"name":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Lester Eastman Conference on High Performance Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LECHPD.2002.1146786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Surface trapping has been identified as a mechanism for lower than expected output power for experimental AlGaN/GaN HEMTs devices. This paper presents dynamic loadline analysis as a means of understanding device behavior that limits large signal performance. From observations of measured data, a model for bias-dependent drain resistance caused by trap-induced space-charge in the ungated region on the drain side of the gate is proposed. This bias-dependent drain resistance model is implemented in conjunction with a Curtice-cubic analytical transistor model to simulate the observed behavior.