A cost-effective scheme for at-speed self-test

Abstract

A serial feedback-based scheme for at-speed self-test is proposed in this paper. By using on-chip feedback lines to link pseudo random pattern generator (PRPG) and multiple input signature analysis register (MISR), aliasing can be reduced, compared to a conventional output register MISR. The analysis of state transition graph (STG) topology revealed that it is possible to design a serial feedback-based built-in self test (BIST) structure yielding STGs of disjunct rings only. Experimental results on ISCAS'85 benchmark circuits are presented.<>