Decoy circuits for FPGA design protection

Abstract

Field-programmable gate arrays (FPGAs) are increasingly used in system designs, but their vulnerability to reverse engineering could lead to lost profits or security breaches. Thus, high FPGA design security is needed with low performance penalties and low realization and maintenance costs. Using a novel circuit modification method, common circuits were augmented with decoy circuits for protection. Security values for the original and modified circuits were calculated, and the original and modified circuits' execution times, power consumptions, and resource usages were collected from simulations. For the modified circuits, security improved by six orders of magnitude, yet execution times, power consumption, and resource usage increased by less than one order of magnitude. The proposed algorithm has demonstrated the potential for substantial increases in FPGA design security at a low cost, and could also be applied to application-specific integrated circuits (ASICs)