A 195 GHz single-transistor fundamental VCO with 15.3% DC-to-RF efficiency, 4.5 mW output power, phase noise FoM of −197 dBc/Hz and 1.1% tuning range in a 55 nm SiGe process

Abstract

A novel approach to design efficient high-output-power fundamental oscillators close to the ƒmax of the employed process is presented. The idea is based on shaping and optimizing the maximally efficient power gain (GME) of the circuit using a pair of internal/external feedback mechanisms. Solving a constrained optimization problem, an optimum pair of passive feedback network is designed to achieve the highest maximally efficient power gain in order to increase the output power and thence the DC-to-RF efficiency. A 195 GHz fundamental oscillator is designed in a 55 nm SiGe process (ƒmax ≃ 340 GHz), which achieves a significantly higher DC-to-RF efficiency (15.3%) among all reported oscillators working above ƒmax/3 of their active devices. The oscillator generates a peak power of 4.5 mW (6.5 dBm) with the best phase noise of −82.3 dBc/Hz and the best FoM of −197 dBc/Hz measured at 100 KHz offset frequency, which is the best phase noise and FoM among all CMOS/SiGe mm-Wave oscillators. The proposed optimization-based method takes into account PVT variations as well as modeling errors of all components in the design process to guarantee the functionality of the fabricated circuit.