Dynamic Bandwidth Management and Information Protection in Service Channels of Non-Stationary Objects

N. Chilikhin, Elena Karpukhina, V. Kutuzov
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Abstract

The paper is devoted to development and integration of the dynamic method of bandwidth management in service (control) communication channels for non-stationary objects. Polar codes (PC) were chosen as a scheme to combat interference in communication channels. Firstly, polar codes allow us to achieve the asymptotically possible bandwidth of a binary channel without memory. Secondly, they have the opportunity to freely choose the required code distance within the framework of the Hamming metric. The Bhattacharyya distance (BD) is used to provide the second advantage. This is a universal mechanism for determining the weight of a matrix row in a common generating matrix for the subsequent allocation of the most “strong/significant” matrix rows and the construction of any code vectors. It is important to note that the paper does not use the classical scheme for determining the likelihood ratio logarithm (LLR) but a modified one. For this purpose, there are used properties of the erasing communication channel (a wide erasure interval), integer values of the likelihood ratio logarithm to minimize computational costs (leveling time delays) and the assumption that the scope of variation changes quasi-linearly in the case of mathematical expectation. The paper describes the switching modes and the mechanism of bandwidth management that is determined by the tasks facing the designer and the operator of the communication system. Simulation was performed on FPGA Xilinx Artix-7 XC7A100T.
非静止对象服务通道的动态带宽管理与信息保护
本文研究了非静止目标业务(控制)通信信道带宽动态管理方法的开发与集成。选择极性码(PC)作为对抗通信信道干扰的方案。首先,极性编码允许我们实现无内存二进制信道的渐近可能带宽。其次,他们有机会在汉明度量的框架内自由选择所需的代码距离。巴塔查里亚距离(Bhattacharyya distance, BD)用于提供第二个优势。这是一种通用机制,用于确定公共生成矩阵中矩阵行的权重,以便随后分配最“强/有效”矩阵行和构造任何代码向量。值得注意的是,本文没有使用经典方案来确定似然比对数(LLR),而是使用了一种改进的方案。为此,使用了擦除通信信道的属性(宽擦除间隔),似然比对数的整数值以最小化计算成本(平衡时间延迟),并假设在数学期望的情况下,变化范围呈准线性变化。本文描述了通信系统设计者和运营商所面临的任务所决定的交换模式和带宽管理机制。仿真在Xilinx Artix-7 XC7A100T FPGA上进行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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