Reconfigurable Multiplicator Over 216, 215 and 214 for DVB-S2X Standard

Abstract

This paper shows that massive streams of data and high data rates requires high-performance digital data-processing systems, development of data transmission optimization methods, optimization of digital filtering and coding/decoding processes. Also forming of reconfigurable parallel multiplicator over Galois field (GF(216), GF(215) and GF(214)) for DVB-S2X standard is described, that allow to reduce number of gates for BCH decoding process. Optimization of formed reconfigurable multiplicator is provided. Corresponding outputs are given.