Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology

Abstract

An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain junction of baseline device can be optimized for only current driving ability and DC reliability. Sometimes this design is not sufficient as ESD protection device including Self-protection output driver device which can be possible long-term reliability issue after ESD stress. Modification of N+ drain junction with LDD spacer mask shows improved ESD performance by reducing the electric field at poly/drain overlap region and, spreading the ESD current path between drain and source. TLP, HBM, DC-IV and, HCI characterization techniques were used to verify the structure and, TCAD simulations were used to examine failure analysis.