Post Simulation of High Speed Sense Amplifiers using 45 nm CMOS Technology Used in IOT Application

Abstract

This work introduces a post simulation of novel sense amplifier component of the memory using 45nm technology node. The proposed design has undergone through physical design in cadence virtuoso EDA tool. The complete memory cell, and the results are analyzed to determine the memory chip performance. The problem of latency, power consumption is solved while introducing three types of sense amplifier such as current mode, voltage mode, and Charge transfer type sense amplifier. The sensing techniques are very much essential in memory systems, CPUs (central processing units), and high-end servers, IOT application, a new sense amplifier (SA) is required. SRAM out performs all other types of memory, including SRAM, DRAM, and non-volatile memories like ROM, PROM, and sense amplifiers. Using 45 nm CMOS technology, a 6T SRAM cell with a unique sense amplifier has been built. The sensing latency and power and Area of various kinds of sense amplifiers is analyzed with lower technology node. By imparting the transistor sizing the various sense amplifiers is analyzed and post verified using cadence virtuoso EDA tool.