Development of an optimised 40 V pDMOS device by use of a TCAD design of experiment methodology

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) Pub Date : 2000-09-06 DOI:10.1109/SISPAD.2000.871262

P. Moens, M. Tack, H. Van Hove, M. Vermandel, D. Bolognesi

引用次数: 4

Abstract

A new medium voltage (40-60 V) pDMOS device has been developed and optimized through the use of a design of experiment (DOE) approach based on TCAD simulations and experimental verification. Layout parameters are varied and the electrical characteristics of the device (e.g. V/sub bd/, specific on-resistance, etc.) together with hot carrier behaviour, are studied as responses. In this way, an optimal device was selected.

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利用实验方法的TCAD设计开发了一个优化的40 V pDMOS器件

采用基于TCAD仿真和实验验证的实验设计(DOE)方法，开发并优化了一种新型中压(40-60 V) pDMOS器件。布局参数的变化和器件的电气特性(例如V/sub / bd/，比导通电阻等)以及热载子行为作为响应进行了研究。从而选择出最优的装置。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)

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