M. Kiyokawa, M. Stubbs, C. J. Verver, C. Glaser, T. Matsui
{"title":"A novel multistage active frequency multiplier","authors":"M. Kiyokawa, M. Stubbs, C. J. Verver, C. Glaser, T. Matsui","doi":"10.1109/ANTEM.2000.7851685","DOIUrl":null,"url":null,"abstract":"A new frequency multiplier, consisting in cascaded single-ended frequency doublers, is proposed as a promising constituent for Ka-band signal sources. Impedance matching at each interstage harmonic frequency is performed directly between transistors by means of a single transmission line. This multiplier translates a low-GHz input signal (∼ 0 dBm), with a conversion gain, into an output as a local oscillator, resulting in eliminated drive amplifiers. The validity of this topology is demonstrated by two, and three-stage multipliers to 14.25 GHz and 28.5 GHz, respectively, developed using medium power (H)FETs.","PeriodicalId":416991,"journal":{"name":"Symposium on Antenna Technology and Applied Electromagnetics [ANTEM 2000]","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium on Antenna Technology and Applied Electromagnetics [ANTEM 2000]","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ANTEM.2000.7851685","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A new frequency multiplier, consisting in cascaded single-ended frequency doublers, is proposed as a promising constituent for Ka-band signal sources. Impedance matching at each interstage harmonic frequency is performed directly between transistors by means of a single transmission line. This multiplier translates a low-GHz input signal (∼ 0 dBm), with a conversion gain, into an output as a local oscillator, resulting in eliminated drive amplifiers. The validity of this topology is demonstrated by two, and three-stage multipliers to 14.25 GHz and 28.5 GHz, respectively, developed using medium power (H)FETs.