High speed PLL frequency synthesizer with synchronous frequency sweep

Abstract

A technique for achieving high switching speed of the phase locked loop circuits is introduced and analyzed. This technique is based on using a pretuned signal that helps the PLL to reach the steady state condition in a relatively short time. This signal is temporally superimposed on the loop filter output to tune the voltage controlled oscillator of the loop. The system mathematical model was derived and proved effective in increasing the system stability and decreasing the settling time. Computer simulation and experimental results confirm the theoretical analysis.